Abstract: The military field often chooses ADI's TS201 chip as the signal processing platform, but because it uses the circuit-switched LINK port to connect, it is difficult to achieve the military's reconfigurable requirements for electronic system design. FPGA can be used to implement the interface conversion function. If FPGA is used to convert the LINK port based on circuit switching to other forms of interface based on packet switching, the DSP system can be reconstructed without changing the hardware connection. This article introduces a reconfigurable signal processing platform based on serial RapidIO technology, and discusses the logic design of the core FPGA. In military electronic equipment such as radar, sonar, and electronic countermeasures, digital signal processors play a vital role as platforms for implementing signal processing algorithms. In the traditional signal processing platform, the military field mostly chooses the DSP chip of TIgerShark series of ADI Company as the signal processing unit, and uses high-speed LINK ports for interconnection within and between PCB boards. The LINK port is a source synchronization interface that can achieve high transmission speeds. However, because the LINK port is based on a circuit-switched interface, both sides of the connection have a single path. Once the LINK port is connected in hardware, the DSP network topology in the system is fixed. Due to the diversity of signal processing algorithms, the direction of data flow in the system is also very uncertain. A fixed DSP topology network can only achieve optimality for certain algorithms. When the direction of data flow changes greatly, the same signal processing platform transmits The efficiency will be greatly reduced. At this time, if the topology of the DSP network can be readjusted, the performance of the platform will be greatly improved. In order to realize the reconfigurable characteristics of the system, it is necessary to use a special FPGA chip to convert the LINK port based on circuit switching into an interface based on packet switching (with routing information) for transmission in other formats. The more popular interfaces based on packet switching are serial RapidIO interface, PCI Express interface and Gigabit Ethernet interface. Serial RapidIO, PCI Express and Gigabit Ethernet technologies can provide high-speed, reliable point-to-point interconnection. Serial RapidIO technology is specifically designed for interconnection of embedded systems. As long as there are enough switches, any topology can be realized. PCI Express technology is designed to focus on the largest compatible PCI bus technology. In order to be compatible with the traditional PCI bus technology, the topology of PCI Express can only be a tree structure. This structure is very suitable for PCs and servers, if appropriate, it can also be used in embedded systems. However, in addition to the need for a switch in the PCI Express structure, a root complex is also required for unified management, which increases the hardware overhead. Gigabit Ethernet technology is an upgrade of 100M Ethernet technology. It was originally used for interconnection in LAN and WAN, which is a very reliable choice for interconnection. However, Gigabit Ethernet technology is slightly less efficient than the previous two technologies, and the system delay is large, which is not suitable for interconnection within real-time embedded systems. Among these three technologies, serial RapidIO technology is the best choice for interconnection in embedded systems [1]. 1 RapidIO technology RapidIO is a high-performance, low-pin-count, system-level interconnection protocol based on packet switching, and is a standard specifically established for the interconnection of various embedded systems [1]. The RapidIO interface is mainly suitable for the connection between chip to chip and circuit board to circuit board. In the version 2.0 specification published by the RapidIO organization in March 2008, the serial RapidIO link can support a transmission rate of 1.25, 2.5, 3.125, 5, 6.25 GBaud per channel [2] (1, 2, 2.5, 4, 5 Gb / s effective data rate). The mainstream configuration that the IP core of the FPGA can support now is an x1 or x4 link, and each channel supports a transmission rate of 2.5 Gb / s or 3.125 Gb / s. Therefore, if you use an x4 link and a 3.125 Gb / s transmission rate, you can achieve 12.5 Gb / s bandwidth in each direction. In addition, RapidIO also provides a higher level of error management and error recovery mechanism, which is a relatively stable and reliable interconnection option [3]. 2 System structure design 2.1 The connection structure of DSP in the board The DSP board is the most basic component module in the signal processing system, and its structure is fixed. This article chooses ADI's TS201 series chips. Each TS201 chip is equipped with 4 high-speed LINK ports, of which 3 LINK ports are used for connection between DSPs in the board, and 1 LINK port is used for protocol conversion through FPGA and converted into serial RapidIO interface to achieve Connection between boards. A total of 6 TS201 chips are used on the board, and its topology is shown in Figure 1. The dotted line in the figure indicates the LINK port connection between DSP chips, and the solid line indicates the LINK port connection between DSP and FPGA. This topology can achieve a higher transmission speed between DSPs in the board, because each DSP can communicate with any other DSP on the board directly or at most once. 2.2 DSP connection structure between boards There are many advantages to using RapidIO interface connection between DSP boards. The most direct benefit is that, because RapidIO uses a serial bus, it makes the wiring design on the back panel no longer difficult, and the system can be expanded even more. More importantly, because RapidIO transmits data in the format of data packets, users can change the flow of data by changing the routing information in the packet header. This makes the reconstruction of the system very easy. The connection of the DSP board in the system is shown in Figure 2. Within the system, a connection can be established between any two (on different boards) DSP chips. For example: if the user wants to send the data in DSP4 on DSP board 1 to DSP6 on DSP board 3, he only needs to register the FPGA internal control routing register (target board ID number) on DSP board 1 in advance when the system is powered on Set to 3, the address assigned by the target DSP is set to 6) can be set through the software. After the switch receives the data, it will send the data packet to the target DSP board according to the routing information configured by the user in the data packet. Then, the FPGA on the target DSP board further sends the data to the target DSP chip. In the next algorithm design, if the data flow direction changes greatly, the user can re-optimize the topology of the DSP network according to the characteristics of the data flow direction to adapt to different algorithms. The process of reconstructing the DSP network topology is difficult to achieve in traditional signal processing platforms. In most cases, because the DSP topology is not flexible enough, the algorithm designer is limited to a fixed DSP topology, which can only reduce the efficiency of the system, thereby leaving a lot of DSP resources idle and reducing the system's processing power. In this new signal processing platform architecture, users only need to set routing information through the software interface to complete the change of the entire platform structure, the system will not reduce the efficiency of the use of algorithm changes. 2.3 Logic design inside FPGA There is a FPGA chip of StraTIx II GX series of Altera on the DSP board. This FPGA chip is specially used to realize the data conversion between the LINK port and the RapidIO interface, and integrates the data of 6 LINK ports into one RapidIO channel. The logical structure of data receiving and sending is shown in Figure 3. When the DSP sends data, the LINK port receiving module of the FPGA buffers the received data in the FIFO, and the data polling state machine checks the storage status of the FIFO in order. When the data in the FIFO meets the maximum load of the RapidIO packet (256 B), the RapidIO data transmission operation is started once. In addition, because the LINK port transmission protocol does not include the data length, the data length transmitted by the LINK port at a time cannot be exactly an integer multiple of 256 B. If there is data below 256 B in the current FIFO, and the LINK port is not currently in transmission, it is also considered that the LINK port has completed one data transmission, and a RapidIO data transmission operation is also initiated at this time. Before starting the RapidIO data transmission operation, the configuration register module will input the corresponding routing information to the RapidIO IP core according to different DSP numbers. RapidIO's IP core is responsible for packaging and sending the input routing information and data together. At the data receiving end of RapidIO, when the RapidIO core receives data, it first checks the target board ID number information in the packet header. If the target board ID number is consistent with the local ID number, it means that the data packet is sent to this board, and then the RapidIO core will pass the received data and DSP address information to the data distribution state machine, and the data distribution state machine will use the address information Distribute the data to the corresponding FIFO. Finally, the LINK port sending module transmits the data to the target DSP. This method of interweaving different signals in different time periods and transmitting along the same channel, and using a method at the receiving end to extract different signals in each time period, similar to time-division multiplexing in communications Mechanisms. 2.4 Functional simulation In order to verify the logic function of the rapidIO IP core and the conversion logic function of the LINK port and the rapidIO interface, td [3: 0] and rd [3: 0] of the two rapidIO cores are connected. One of the backends of the rapidIO core is connected to the control logic for sending data packets, and the other backend of the rapidIO core is connected to the control logic of receiving data packets. Connect the LINK port logic, interface conversion logic and rapidIO core logic in series, and then apply an excitation signal at the data sending end to perform data verification at the data receiving end. The whole process is shown in Figure 4. In the simulation process, the most critical part is to verify the logic function of rapidIO core. The logic layer interface of rapidIO IP core provided by Altera Company conforms to the interface timing of the avalon bus [4] ). The control of rapidIO core can refer to Avalon specification [5]. 2.5 Defects and solutions In the system, each LINK port achieves a bandwidth of 300 MB / s. If 6 LINK ports simultaneously send data, the total bandwidth will reach 14 Gb / s, which has exceeded the maximum bandwidth supported by RapidIO's IP core. At this time, the RapidIO link will become the bottleneck of data transmission, resulting in a reduction in the transmission rate of the DSP. In addition, when less than 3 DSPs send data, it will cause the waste of RapidIO link. This is like the traffic in a big city, the road will be congested during commuting hours, and at other times, the road will be unobstructed. In life, many people will avoid traveling during peak hours. Similarly, when using this system, one should try to avoid sending data from 6 DSPs to other boards simultaneously on one DSP board. This paper presents a reconfigurable signal processing platform built using RapidIO technology, and briefly introduces the realization of its logic function. The biggest advantage of this platform is the reconfigurability of the system. Using such a signal processing platform, DSP engineers can rebuild a more optimized DSP network topology based on the data flow of different algorithms, thereby improving data transmission efficiency. In short, the reconfigurable signal processing platform can flexibly change the topology of the DSP network in the system to adapt to the application of various data flows, saving users and the country a lot of equipment purchase costs and development time. battery pack current sensor,battery current sensor function,battery current sensor test,allegro current sensor Shanghai Zhilong Electronic Technology Co.,Ltd , https://www.zhilongsensor.com