Overview:

In order to solve the problem of computer system power supply retention time, ensure that the output voltage is stable within a certain range for a period of time. Make sure that the computer has enough time to back up data or switch to an uninterruptible power supply (UPS) in the event of an input failure. To this end, a composite single-switch PFC pre-regulator is proposed and designed according to requirements. This design can reduce the capacity of the storage capacitor and make the output current harmonic meet the requirements of IEC1000-302. The conventional APFC converter can be divided into two types and two types, and the two-stage type PFC converter includes a PFC pre-regulator of the front stage and a DC/DC converter of the latter stage. The output voltage of the PFC pre-regulator is regulated at 380 V. Because the asymmetric half-bridge (AHB) converter is simple in structure and has zero voltage switching characteristics, the capacity of the CPFC needs to be large enough to ensure that the input voltage of the AHB converter does not change much during the hold time, in order to reduce the capacity of the CPFC. A first-order Boost converter is added between the PFC converter and the AHB converter to solve the problem. 1 DC/DC converter applied to the latter stage is generally applied to the two-stage PFC AC/DC converter of the latter stage as shown in Fig. 1. Figure 1. Two-stage PFC AC/DC converters require a certain hold time for power supplies in most computer systems. The hold time is the time during which the power supply keeps the output voltage stable within a certain range after the input voltage is suddenly turned off. This requirement ensures that the computer has enough time to back up data or switch to an uninterruptible power supply (UPS) in the event of an input failure. During this time, energy is supplied to the load by the storage capacitor CPFC in the power supply. Because there is no energy input after the input is powered off, the voltage across the CPFC will gradually drop to zero. Thus, the input voltage of the DC/DC converter of the latter stage will change too much, but the input voltage variation range of the AHB converter is relatively small, and it is responsible for losing some of her advantages. Therefore, the capacity of the CPFC needs to be large enough to ensure that the input voltage of the AHB converter does not change much during the hold time. Figure 2 Three-stage PFCAC/DC converter In order to reduce the capacity of the CPFC, a first-order Boost converter is added between the PFC converter and the AHB converter, as shown in Figure 2. Under normal operating conditions, the first stage converter performs power factor correction, and the added Boost converter operates as a DC/DC stage in current continuous mode. When the input is powered down, the added Boost converter can transfer all the energy stored on the CPFC to the load, thus greatly reducing the capacity of the CPFC. However, the three-stage structure shown in FIG. 2 is too complicated, which increases the cost and volume of the circuit and is not efficient. In order to simplify such a three-stage structure, the first two sets can be one stage, and a composite single-switch PFC presetter is proposed for this purpose. (Please read the PDF for details)