In the era of mobile computing, the design of system-on-a-chip (SoC) has become more complicated because of the many challenges in the design process, such as the need to follow complex design rules for advanced process nodes, using low-power circuit design techniques, and The size of the amplifier circuit. Power integrity is one of the key factors in designing a successful design. This article introduces a new tool that, compared to other existing technologies, not only increases the speed of power integrity analysis and signoffs by a factor of 10, but also achieves an accuracy similar to the Integrated Circuit General Simulation Program (SPICE). degree. The tool integrates a complete set of design implementation and sign-off tools to better overcome the challenges encountered during the sign-off process, enabling the industry's fastest design closure process. Introduction In order to meet the various requirements of mobile computing, the design of system-on-chip has become more and more complicated. As consumers begin to favor devices that are smaller, perform better, and have longer battery life, the chips used in the device must provide richer features, lower power consumption, and smaller size. For design engineers, these changes mean that they must use advanced power technologies (such as power control switches), add intellectual property content and functionality (such as analog/mixed-signal macros), and reduce design margins during the design process ( For example, the power supply voltage is less than 1V). On the other hand, the product launch cycle has become shorter and shorter, so in the final stages of the design cycle, the power sign-off is critical to the successful delivery of the design to manufacturing. To date, the available power sign-off technology has not kept pace with innovation. For example, the extra runtime has been a bottleneck that prevents designers from fully and comprehensively performing power integrity analysis and optimization. However, there is now a new tool that can solve this problem by using advanced massively parallel algorithms and hierarchical structures to increase power integrity analysis and signoff times by a factor of 10, while still achieving SPICE-like accuracy. degree. In addition, as part of a complete process from chip to system, the tool accelerates the design convergence process by increasing productivity throughout the design cycle. Increasingly complex product design eliminates the need for new tools for power integrity analysis Product design is becoming more complex, product sizes are getting smaller and smaller, and the requirements for product analysis are becoming more complex, which increases the time required to complete power integrity analysis and sign-off. If you use the "flat" design approach to flatten the design to a high-level layer, it's not enough to analyze a very large-scale design with hundreds of millions of instances. Current solutions tend to divide design analysis into multiple parts that correspond to "single point tools," which do not meet the requirements of advanced system-on-chips in terms of accuracy or ease of use. In addition, because the current solution uses a single-point tool, the impact of the power supply on timing closure cannot be effectively evaluated, while timing is most sensitive to the power supply (VDD). In addition, advanced node design techniques and techniques such as FinFET process and 3D-chip (3D-IC) packaging pose new challenges. For example, with the deployment of FinFET devices, new electromigration rules are created due to factors such as vertical current direction, increased power density, and the like. With the deployment of three-dimensional stacked chips, there will be new demands for electrothermal co-simulation. In order for design engineers to meet the requirements of the time-to-market and product quality, a complete power integrity analysis solution covering the chip, package and system is required. What features does a perfect power integrity analysis tool need? A design may fail when there are scenarios such as increased leakage, temperature changes, or a drop in operating voltage due to static and dynamic IR drops. Whether it's for millions of gate-level designs or for multiple bare crystals, debugging power supply and IR drop constraints at the early stages of design and verifying compliance is critical to saving valuable development costs and time. In other words, finding the "hotspot" on the chip as early as possible helps prevent chip performance degradation (Figure 1). In order to better support advanced system-on-chip design, the perfect power integrity analysis tool should have the following features: ◠Can calculate leakage on the chip as well as switch and internal energy consumption; ◠Ability to analyze the power integrity of the power network (IR voltage drop detection and electromigration detection); ◠Provides recommendations on the optimal size and arrangement of decoupling capacitor units and power control switches in the circuit to optimize the physical implementation current in the design; • Ability to evaluate the effects of IR drop on design convergence, including static timing analysis. Using proven algorithms and engines with proven quality in the production process, Cadence has developed a new power integrity analysis tool that can cover both the entire chip and all the cells on the chip (ie Voltus IC) Power Integrity Analysis Solution), which provides all of the above features. It analyzes up to 10 times faster than competing solutions and provides SPICE-like accuracy. In addition, Taiwan Semiconductor Manufacturing Co., Ltd. (TSMC) has verified the performance of this tool through the 16nm FinFET process. Therefore, engineers can believe that the tool can give accurate analysis results across different design rules.
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