The previous article briefly introduced some basic concepts about the Transaction Layer and Data Link Layer of the PCIe bus. This article continues to talk about the bottom layer of the PCIe bus - the Physical Layer. In the PCIe Spec, the physical layer is divided into two parts, which are the physical layer logic sublayer and the physical layer electrical sublayer. The latter is generally implemented using SerDes. This article just briefly introduces some basic concepts of PCIe physical layer. For detailed and in-depth introduction to the physical layer, please pay attention to my follow-up serial blog post. Since the physical layer is at the bottom of the PCIe architecture, both the TLP and the DLLP must complete the sending and receiving operations through the physical layer. TLPs and DLLPs from the data link layer will be temporarily put into the physical buffer and added with Start & End Characters. These start characters are sometimes called Frame Characters. ). Specifically as shown below: Note: The TLP and DLLP mentioned here refer to the packet sent by the original sender of the packet, that is, the TLP indicates that the original sender of the packet is the transaction layer, and the DLLP is the data link layer. However, the TLP will still be forwarded by the data link layer and add Sequence and LCRC. One of the important functions of the physical layer is 8b/10b encoding and decoding (Gen1 & Gen2). Gen3 and later PCIe uses 128b/130b encoding and decoding mechanisms. About 8b/10b, it is not described in detail here. Another important function of the physical layer is to perform initialization and training of the link (Initialization & Training), and it is a completely automatic operation and does not require human intervention. After the link is initialized and trained, some basic attributes of the current PCIe device can be determined: The width of the link (Link Width, x1 or x2, x4...) · Link Data Rate · Lane Reversal - Lanes connected in reverse order · Polarity Inversion – Lane shape connected backward · Bit Lock Per Lane – Recovering the transmitter clock · Symbol Lock Per Lane – Finding a recognizable position in the bit-stream · Lane-to-Lane De-skew Within a Multi-Lane Link The electrical layer of the physical layer mainly implements differential transmission and receiving pairs, as shown in the following figure: Because of its high speed, AC-Coupled is used. To put it plainly, a capacitor Ctx is added to the signal line. Both the low-frequency signal and the DC signal are suppressed. It should be noted that PCIe physical layer processing can forward LTP and DLLP, and can also directly send Ordered Sets. It is called a command set because it is not a true packet because the physical layer does not add Start & End Characters. And the command set starts at the physical layer of the sender and ends at the physical layer of the receiver. Although the command set does not have a start character, for the Gen1&Gen2 version of the PCIe physical layer, a character called COM is added as a start character, followed by three or more information characters. Note: PCIe Gen3 and later versions are handled differently, but Gen3 is backwards compatible with Gen1 & Gen2. Since this article is mainly based on Gen2, you can refer to PCIe Gen3 Spec for more information on Gen3. The command set (Ordered Sets) transceiver diagram, as shown below: The structure of Ordered Sets is shown below: The command set is mainly used for Link Training Process. In addition, the command set is also used for the operation of the link to enter or exit the low power mode.
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