TTL gate circuit 1. TTL NAND gate circuit (1) Circuit structure and working principle TTL NAND gate is the basic form of TTL logic gate. The typical TTL NAND gate circuit structure is shown in Figure 8-16. The circuit consists of an input stage, an inverting stage, and an output stage.
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Figure 8-16 TTL NAND gate circuit and its logic symbol The input stage consists of a multi-emitter transistor T1 and a resistor R1. Think of the collector junction of T1 as a diode and the emitter junction as two diodes back to back with the former. Thus, the role of T1 and the function of the diode and the gate are exactly the same.
The inverter stage consists of a transistor T2 and resistors R2, R3. Two opposite phase signals are provided through the collector and emitter of T2 to meet the requirements of complementary operation of the output stage.
The output stage is a "push-pull" circuit consisting of transistors T3, T4, diode D and resistor R4. When T3 is turned on, T4 and D are turned off; when T3 is turned off, T4 and D are turned on. The effects of the inverting stage and the output stage are equivalent to the function of the logical NOT.
At least one of the inputs A and B is zero. Let A be 0, its potential is about 0.3 V; the rest is l, its potential is about 3.6 V. T1 corresponds to the conduction junction of the input terminal connected to the low potential, and the forward conduction voltage of the emitter junction is set to 0.7 V. At this time, the base potential of T1 is: 
This voltage acts on the collector junction of the T1 tube and the emitter junction of T2 and T3. It is obviously impossible to turn on T2 and T3, so both T2 and T3 are in the off state. Since T2 is turned off, its collector potential is close to the power supply voltage U CC , thus turning T4 and D on, so the potential at the output terminal Y is: 
It implements the logical relationship of "the input has low and the output is high".
Inputs A and B are all 1 (set the potential to be approximately 3.6 V). UCC provides a base current to T2 through the collector junction of R1 and T1 to saturate T2, thereby further saturating T3. The potential at the output Y is: 
It implements the logic function of "Input full height, output low". At this time, the collector potential of T2 is: 
T4, D must be cut off.
In summary, when any input in the T1 emitter is 0, the output of the Y terminal is 1; when the input of the T1 emitter is all 1, the output of the Y terminal is 0. Achieved the function of NAND. Pay attention to the problem of floating at the input when using TTL circuits. When the T1 emitter is completely floating, the power supply UCC can still supply the base current to T2 through the R1 and T1 collector junctions, causing T2 and T3 to turn on, T4 and D to turn off, and the Y terminal output to be zero. When there is 0 input in the T1 emitter, and the rest is left floating, the emitter of 0 input still determines that T2 and T3 are off, T4 and D are on, and the Y output is 1. It can be seen that the TTL circuit input is suspended at the equivalent of 1.
(2). Main external characteristic parameters The parameters are the basis for us to understand the performance of TTL circuits and use them correctly. The following only briefly describes several parameters that reflect the main performance of TTL and non-gate circuits.
1 0 outputs a high level U OH .
When the NAND gate has at least one input terminal connected to a low level, the value of the output voltage is referred to as the output high level UOH. The product specification value is U OH ≥ 2.4 V.
2 0 output low level U OL .
When all inputs of the NAND gate are connected to a high level, the value of the output voltage is called the output low level UOL. The product specification value is U OL ≤ 0.4 V.
3 0 fanout factor No.
The number of input terminals of the next-level gate that can be connected to the output of the gate circuit is called the fan-out coefficient No of the gate circuit, which is also called load capacity. Generally No ≥ 8.
4 0 average transmission delay time tpd.
When a pulse voltage is applied to the input of the NAND gate, the output voltage will have a certain time delay to the input voltage. The time from 50% of the rising edge of the input pulse to 50% of the falling edge of the output pulse is called the rising delay time. Tpd1; The time from 50% of the falling edge of the input pulse to 50% of the rising edge of the output pulse is called the falling delay time tpd2. The average transmission delay time tpd is defined as the average of tpd1 and tpd2, namely: 
The average transmission delay time is an important parameter to measure the NAND gate switching speed. The smaller the value of this parameter, the better. In addition to NAND gates, TTL gates also have a variety of different functions such as gates, OR gates, NOT gates, NOR gates, XOR gates, and so on. As shown in Figure 8-17, several commonly used TTL gate chips are introduced.
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