Binocular vision ADAS chip - S32V234 This article refers to the address: http:// The S32V234 uses four ARM Cortex A53s as the core CPU for higher performance per watt. An ARM Cortex M4 is used as an on-chip MCU for real-time control of critical IOs such as CAN-FD and supports the AutoSAR operating system. The chip contains a programmable image signal processor (ISP), so the matching image sensor can output raw data, which reduces material costs and saves space. In addition, the chip also contains two visual acceleration engines called APEX2CL. Each APEX2CL has 64 local computing units (CUs) with local memory and dedicated DMA to accelerate the image recognition process through SIMD/MIMD (Single Instruction Multiple Data/Multiple Instruction Multiple Data). It is also worth noting that, considering the stringent requirements of the ADAS system for safety and reliability, the S32V234 incorporates such things as ECC (Error Checking and Correction), FCCU (Fault Collection and Control Unit), M/L BIST (design). A variety of security mechanisms, such as memory/logic built-in self-test, can meet the requirements of ISO26262 ASIL B~C. The advantages of binocular vision ADAS Compared to monocular vision, the key difference between Stereo Vision is that dual cameras can be used to image the same target from different angles to obtain disparity information and estimate the target distance. Specific to visual ADAS applications, if a monocular camera is used, in order to identify targets such as pedestrians and vehicles, large-scale data acquisition and training are usually required to complete the machine learning algorithm, and it is difficult to identify irregular objects; Although the accuracy of the laser radar for ranging is high, the cost and difficulty are also high. The biggest advantage of binocular vision is to achieve target recognition and ranging with certain accuracy under the premise of low development cost, and complete ADAS functions such as FCW (forward collision warning). The basic principle of binocular vision ranging is shown in Fig. 2: the parallax of the target point P in the two cameras is d=EC+DF, and the derived distance z=(fq)/d is derived according to the similarity of the triangles. The focal length f and the camera optical axis distance q can be regarded as fixed parameters, so that the distance z can be obtained by obtaining the parallax signal d. Binocular vision ranging step Camera calibration Image acquisition Image preprocessing Feature extraction and stereo matching 3D reconstruction Among them, the camera calibration is to obtain the camera's internal and external parameters and distortion coefficients, etc., which can be performed offline; the synchronization of the left and right camera image acquisition, the quality and consistency of the image preprocessing, and the stereo matching (acquisition of disparity information) and 3D reconstruction (Acquisition of distance information) The huge computational complexity of the algorithm's real-time requirements poses a challenge to achieve binocular vision ADAS on embedded platforms. Application of binocular vision ADAS The S32V234 has two MIPI-CSI2 camera interfaces, each providing a maximum transfer rate of 6 Gbps, which can be used for video input of two left and right cameras. Since the two cameras input two MIPI channels separately, it is necessary to consider the synchronization problem between the two. With the cooperation of external image sensors, the S23V324 can support different synchronization methods. As shown in Figure 3, the image sensor typically has a field sync signal (VSYNC) and a line sync signal (HSYNC) for signal synchronization: 由 When the two cameras work in the master-slave mode, the master sends a sync signal to the slave. ⊿ When both cameras are in slave mode, the sync signal can be generated by the S32V234 internal timer and sent to both cameras. After the S32V234 acquires the image signal of the external camera, it can be preprocessed by the internal ISP. The ISP module contains multiple internal processing units that use on-chip SRAM to buffer input signals and intermediate results, and a dedicated coprocessor to manage the timing of the ISP processing unit for pipelined ISP processing. The built-in ISP not only saves the cost of the two-way camera, but also its computing resources and bandwidth can support the real-time processing of the two-way high-definition image signal, ensuring the quality and consistency of the two-way image signal. Binocular vision ADSA solution In binocular vision ADAS applications, the biggest challenge comes from the huge amount of computation required for stereo matching and 3D reconstruction of two-way images. Taking the FCW application as an example, the extraction of the disparity signal is required to have sufficient accuracy to ensure the ranging accuracy, and the processing frame rate is required to maintain a certain level to ensure the response speed of the early warning. Therefore, the embedded platform is required to have sufficient processing capability. The structure of the image acceleration engine APEX2 integrated in S32V234 is shown in Figure 4. Its parallel computing structure, local memory and dedicated DMA design ensure extremely high processing efficiency for image signals. After the ISP preprocesses the image signal, it is sent to the DDR. The APEX2 engine divides the image and sends it to the local memory CMEM corresponding to each CU via a dedicated DMA. The algorithm such as block matching (Block Matching) required for stereo matching can be performed. Parallel processing in different CUs, the processed data is sent back to the DDR via DMA, further processing by the CPU (such as generating an early warning signal), or sent to a dedicated DCU (Display Control Unit) module output display. In summary, the data flow of the binocular vision application based on S32V234 is shown in FIG. 5. In this application, the data flow flows in the direction of ISP-APEX2-DCU, and A53 acts as the master CPU to complete the logic control and necessary data processing. Through this pipelined processing method, each part of the computing resources can be fully utilized. The S32V234 development board is used to build a binocular vision platform to process dual-channel 720p@30fps video signals. The output is shown in Figure 6. The distance between the target and the camera in the three images from left to right is 1m, 2m, and 3m, respectively, and the display results represent the target distance with changes in the warm and cold colors. The results show that the S32V234 can process the binocular vision signal in real time, and correctly obtain the three-dimensional ranging result. At the same time, the safety design of the chip can meet the requirements of the binocular vision ADAS system. to sum up NXP's visual ADAS chip S32V234 integrates image signal processor ISP, graphics acceleration engine APEX2, 3D GPU and other dedicated computing units to make full use of heterogeneous computing resources through a pipelined processing architecture. The support of different computing modules for various APIs such as OpenCV, OpenCL and OpenVG enhances the portability of the algorithm. The functional safety design according to ISO26262 allows the chip to meet the stringent safety requirements of the ADAS system. The S32V234 supports a wide range of visual ADAS and sensor data fusion solutions including binocular vision, making us a solid step on the road to driverlessness. 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