From smartphones, laptops, and servers related to a variety of cloud applications, flash storage is ubiquitous in our real world. Flash memory technology has become so common that most of us don't even realize that flash memory technology is not a reliable storage medium in nature. In fact, the life of a flash memory unit is limited, and the characteristics of flash memory mean that a strong wear-leveling technique is required to make it perform better.

The good news in the industry is that the wear leveling technology in modern flash memory controllers has made significant advances to overcome the inherent weaknesses of flash memory storage media and to help out the advantages of flash memory. For modern flash memory storage systems, the choice of controller is more important than the flash memory storage itself. By selecting the appropriate flash memory controller for application, the system's durability and reliability can be improved.

This is a significant benefit for end users and equipment manufacturers, because with the right high-quality controllers, low-cost, high-capacity, multi-level MLC flash memory can be used more critically. In the application.

Since almost all of the electronic devices that are in contact today use flash memory storage, it's easy to forget that the technology itself is a demanding medium and faces many reliability challenges.

The limited number of P/E times is the biggest challenge. Although flash memory storage units can be read close to infinite number of times, the number of times they are programmed or erased (P/E) is very limited. The durability of flash memory being programmed or erased depends on the type of flash memory storage. In general, for most NAND flash memory storage devices such as SSD or eMMC, commercial MLC type is used. Flash memory, usually with only a few thousand program or erase cycles per cell.

Although the flash memory does not have much problem when reading, the flash memory write process is more involved. Flash memory can be written at the page level in kilobytes. The page must be kept clean before the data is written correctly. Unfortunately, the flash memory can only erase one block at a time, and its size is megabits. Therefore, it is first necessary to erase the large block memory including the page before writing to the flash memory. Since updating a unit of flash memory requires updating all of the cells in the block, this will shorten the overall life. This process is commonly referred to as Write Amplifica (TIR).

In order to reduce wear on the flash memory storage unit, all flash memory storage devices must use wear leveling techniques. These techniques are designed to evenly distribute wear on the drive to maximize system durability. Temporary buffers in DRAM, SRAM, or unused flash memory cells can be used to track where the drive will be written next and the old location that needs to be erased.

Another major issue with flash memory drives is power failure protection. The temporary buffer contains information such as the data that the drive should write next and the old location that must be erased. These messages are stored in memory that is easily lost. In this case, a sudden power failure will cause the buffer to be erased, causing the transfer. Data failures cause catastrophic losses.

As the size of lithography processes decreases and the density and performance of flash memory storage increases, the last issue affecting the reliability of flash memory is the ever-increasing number of errors. The original flash memory drive used single-level cell (SLC) flash memory, where each cell stores one bit, but modern flash memory drives typically divide a flash memory cell into multiple bits, ie MLC/TLC fast Flash memory. Each physical unit supports more bytes to increase the storage density, but reduces the threshold between each byte on/off state. This not only increases the bit error rate but also reduces the lifetime. As the size of the lithography process decreases, the density of the flash memory is further increased and the error rate is also increased.

Advanced Controller Technology Improves Reliability While flash memory storage reliability faces these challenges, we can still use it for everyday consumer, commercial, and even mission-critical applications, primarily thanks to advanced fast Flash memory controller technology. These controllers combine advanced technologies in wear leveling, power failure management and error correction to enable us to safely and reliably use today's high-density flash memories.

Wear Balanced Flash Memory Conversion Layer (FTL) is the most important aspect of flash memory controllers. By converting the logical address of the host to the physical address on the flash memory, the SSD can be worn out. For example, if the host system updates the data at the same address, the FTL will convert the logical address to a new physical address to evenly distribute the wear on the flash memory drive, greatly improving durability.

The granularity of FTL mapping logic to physical addresses has a large impact on performance and durability. Simpler flash memory media, such as consumer USB and SD cards, use block-based mapping to perform mapping at the block level (in millions of bits). Since each logical page maps directly to a fixed physical page, wear leveling occurs at the block level, and optimization is not possible at the page level.

Since the size of the block is the smallest size of the erase operation, this mapping is very simple to implement and has a low burden. However, this simple method results in a large amount of write amplification and shortens the life of the component.

Page-based mapping is typically used in modern SSDs, which are physical pages that map finer-grained logical data pages (in thousands of bits) to data. Through this mapping, logical pages can be mapped to any physical page within the block while achieving wear level balancing at the block and page levels. However, for other form factors, SSD-based page mapping has not been widely used.

More granular methods such as page mapping require more computational power and must store larger mapping tables. However, increasing particle size can significantly reduce write amplification.

Especially for industrial, embedded or IoT applications, smaller random I/O operations are normal, granularity, page mapping can greatly reduce write amplification and extend the life of the device.

Power-off protection Because the mapping information of the SSD wear-balance algorithm is usually stored in DRAMs that are prone to drain, power failures can lead to catastrophic message loss and drive damage. To prevent this possibility, many industrial SSDs use supercapacitors to store backup power in case of power failures, giving the system time to dump DRAM content into flash memory that is not easily lost.

Although this method is feasible, it is not ideal. Relying on the backup power of supercapacitors, these SSDs not only increase the cost, but also introduce additional points of failure, thus affecting the reliability and service life of the system. Smaller forms of devices such as micro SD (μSD) are not allowed to include DRAMs and capacitors at all.

Storage devices with Hyperstone hyMap technology flash memory controllers can store mapped messages directly in non-volatile memory, which not only eliminates the cost of DRAMs and capacitors, but also ensures data security at all times and under all circumstances.

Error correction is the last step in the reliability of flash memory storage.

Previous flash memories could use a simple Hamming-Code error correction code (ECC), but a new generation of high-density MLC flash memory requires more error correction. Modern MLC ECCs must be able to correct multiple bits per sector.

Consumer SSDs may choose to use this lower quality LDPC code to perform this type of ECC, but industrial grade flash memory has more stringent requirements and prefers BCH or other higher reliability methods. With 96-bit BCH ECC, multi-bit error correction can be provided without any burden on I/O operations.

The remote control is a challenge for building reliable flash memory for high reliability/long life critical. Although solid-state storage has no moving parts, it is physically more reliable than a hard disk. However, the limited lifetime of flash memory cells, power failures, and error correction of flash memory pose challenges to data reliability, especially for applications that require long life cycles, such as embedded and industrial drivers.

In the past, simply purchasing an SLC-type flash memory was enough to ensure a relatively reliable system. However, as process geometries shrink and flash memory density continues to increase, the differences in reliability and error rates between different flash memory media today are not as obvious as they were before, and the biggest determinant of today's storage system reliability is instead The design of the flash memory controller.

For applications that require high reliability and long life, it is important to choose controllers in the embedded industrial market rather than those that deliver high performance at the expense of lifetime or data integrity. With advanced wear leveling technology, power fail-safe design and powerful ECC, Hyperstone controller-based storage devices ensure a highly reliable solution.

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