In today's highly developed integration, it is impossible to solve the problem by multiple crystal sources, and once the crystal is fixed, its flexibility and portability will be greatly affected, so some clock crossover chips have emerged. Today we will A typical application of the representative AD9522 clock crossover chip is used to achieve a role. 1. External characteristics The AD 9 5 2 2 is a multi-channel clock output and distribution function that supports sub-picosecond jitter performance and integrates PLL (PhaseLockedLoop) and VCO (Voltage Controlled Oscillator) inside the chip. The tuning range of the VCO is 2.02GHz~2.335 GHz. The AD9522 serial interface supports the data bus of SPI and I2C. The internal EEPROM of the chip can be programmed through the serial port, which can be used to store the user-configured register data to divide the input clock. The AD9522 has 12 channels of LVDS level output, which can be divided into 4 groups. Each group has a frequency divider. The division ratio can be set freely within the range of 1-32. As shown in Figure 1. 2. Internal characteristics The input clock external to the AD9522 is supplied by the crystal. The multiplication and division of the internal clock are controlled by the phase-locked loop PLL and the voltage-controlled oscillator VCO. For example, the voltage controlled oscillator gives a signal, one part is used as the output, and the other part is phase-compared with the local oscillator signal generated by the PLL. In order to keep the frequency constant, the phase difference is not changed, if there is a phase difference change. Then, the voltage at the voltage output end of the PLL changes, and the VCO is controlled until the phase difference is restored to achieve the purpose of frequency locking. As shown in Figure 2.
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