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How to reduce DPWM jitter of UCD30xx series digital power controller

The UCD30xx family of digital power controllers includes the UCD3040, UCD3020, and UCD3028, which are primarily used in AC/DC power supplies and isolated direct-transform (DC/DC) power supplies. The principle of digital power supply and analog power supply is the same, but the value used by digital power supply is digital, which is the value after the analog quantity is discretized, so the inevitable precision will be lost. Observing the falling edge of UCD30xx digital pulse width modulation (DPWM), it will be found that the DPWM falling edge has jitter when the power supply is running steady state (the oscilloscope is triggered by the rising edge); and the DPWM falling edge jitter range is different according to the loop bandwidth. It will also be different, the bandwidth will be high, and the jitter will be small. For most applications, there is no problem, but if the bandwidth requirements are high, then the jitter range will be large, and if it is serious, the transformer noise will exceed the standard. This article focuses on how to use the analog zero-pole method to reduce the DPWM jitter range without reducing the system bandwidth.

There are two cases that can cause the DPWM falling edge to have a large jitter range: 1. The UCD30xx has poor power supply; 2. The UCD30xx digital compensator has a high bandwidth. If the UCD30xx supply is unstable, the DPWM falling edge jitter is approximately 100ns. Unless the power supply is improved, the jitter range cannot be reduced anyway. Because most applications use LDOs to power the UCD30xx, there is no power instability, so this article focuses on the impact of UCD30xx digital compensation loop changes on jitter. Figure 1 shows the DPWM falling edge jitter waveform of a power supply using the UCD30xx as the primary controller. As can be seen from the figure, the DPWM falling edge jitter range is approximately 166ns. In addition to the large noise caused by the DPWM jitter, this power supply meets various requirements. The UCD30xx can flexibly configure the poles. This article mainly introduces how to use the external analog poles and poles combined with the UCD30xx internal poles to reduce the jitter of the UDC30xx output DPWM falling edge without changing the required loop bandwidth.

UCD30xx digital compensation loop

The UCD30xx family of controller digital compensation loops is implemented with a configurable hardware compensation loop. The hardware compensation loop can be configured as 2 zero 2 pole (2P2Z) or 3 zero 3 pole (3P3Z) compensation. 3 Zero point 3 The pole is realized by 2 zero point 2 poles (corresponding coefficients: 01 b , 11 b , 21 b , 11 a , 21 a ) plus 1 zero point 1 pole (corresponding coefficient: 12 b , 12 a ). For the switching power supply, the compensation method of 2 zero point 2 pole is mainly used. Figure 2 shows the internal block diagram of the hardware compensation loop of the UCD30xx series controller.

From Figure 2 we can get the transfer function of the compensation loop in the z (discrete) domain, as shown in equation (1):

We only need to configure the five coefficients 01 b , 11 b , 21 b , 11 a and 21 a , then the hardware compensation loop can start working . Because it is a hardware circuit, it is not limited by software resources. Once the hardware compensation loop is enabled, it is automatically executed without being affected by the software unless the software actively modifies it.

The above is part of the content, more content can be found in the PDF document Chinese manual!