1 Introduction: The position of power consumption in chip design For a long time, the biggest challenge designers face is timing closure, and power consumption is in a secondary position. In recent years, the following factors have made power consumption increasingly attractive to designers: 1) The rise of mobile applications has made the importance of power consumption gradually appear. Large power consumption means shorter battery life. 2) The improvement of chip integration makes the design of power supply system a challenge. As the process progresses, the circuit density within the chip doubles and runs above several times the frequency, while the on-chip wiring becomes thinner and finer, and the on-chip power supply network must have more power with fewer connections. Line resources are sent to each unit. If this is not possible, the stability of the chip and the predetermined operating frequency will become a problem. The IR voltage drop and the large amount of wiring resources consumed by the power supply network have become an important issue for the back-end designers, and this pressure is now being passed on to the front-end designers step by step, requiring less power to be needed during the design phase. 3) The impact of power consumption on cost is increasingly significant The power consumption determines the heat generated by the chip, and the package structure needs to transfer the heat generated by the chip in time, otherwise the temperature rises, and the circuit cannot work stably. Therefore, a chip that generates a large amount of heat needs to select a package form with good heat dissipation, or an additional cooling system such as a fan, which means an increase in cost. Based on the above reasons, power consumption has become an important indicator and constraint of products. The following factors should be included in the designer's consideration at the beginning of the design: 1) Determination of power consumption target a) the commercial value of power consumption indicators in the application area of ​​the product; b) the cost impact of packaging and process; c) the feasibility and complexity of the implementation, and the resulting assessment of design risk and time-course impact; d) Selection of reference values: determined according to similar products, empirical values, tool analysis, and continuously revised as the design progresses. 2) Optimization plan (strategy) setting Before further analysis, let's look at the composition of power consumption. 2 power consumption components 2.1 core power The power consumption consists of four parts: RAM, ROM, clock tree, and core logic. 1) RAM The calculation of RAM power consumption is a complex task. Fortunately, the memory compiler can do this for us. The key point is the rate at which each port is accessed, which can be obtained by considering the access pattern type, or by simulation. It is recommended to generate RAM/ROM power consumption data for different parameters (width, depth, speed, port number) at the beginning of the design to facilitate design exploration. 2) Clock tree The power consumption of the clock tree accounts for 40% to 60% of the power consumption of the entire chip because its high activity rate (100%) and positive and negative edges consume power. Among them, the capacitor contains the capacitor of the register, the capacitance of the driving unit and the wiring capacitance. 3) core logic circuit Define the core logic circuit power consumption as the combination of the clock tree and the power consumed by the timing unit. It consists of two parts: Leakage current capaciTIve loads 4) Macro cell Most chips contain analog macros such as PLLs, which can be found in the library's data sheet. Designers can turn off modules that do not need to work by splitting the system mode to reduce power consumption. 2.2 IO power IO power consumption includes IO units, external loads, external terminals, and so on. Because of the need to drive board-level wiring, the IO's capacitance can be hundreds of times larger than the internal unit, thus consuming more power. Sometimes, the power consumption of IO can account for a large proportion of the overall power consumption, and the system architecture may change, such as: redefining the division of the system to reduce the chip-chip connection; selecting different IO interface protocols to reduce energy consumption. IO power consumption is usually determined by the system architecture, interface bandwidth, and protocol requirements. Once the library is selected, the space that the designer can optimize is small, but the power consumption of the core can be reduced by the designer. In the following pages, we will focus on the estimation and optimization of the core power consumption. Shenzhen E-wisdom Network Technology Co., Ltd. , https://www.healthy-cigarettes.com