1 Overview The TLC1549 series is a serial-controlled, continuous successive approximation analog-to-digital converter manufactured by Texas Instruments. It uses two differential reference high-impedance inputs and a three-state output to form a three-wire interface. The three-state outputs are slices. Select (CS active low), input/output clock (I/O CLOCK), data output (DATAOUT). The TLC1549 pin arrangement is shown in Figure 1. TLC1549 can be sent to the microcontroller in serial mode, and its functional structure is shown in Figure 2. Because TLC1549 uses CMOS technology. Internally with automatic sample-and-hold, scalar-scaled conversion range, noise immunity, and switched capacitor design for a total error of only ±1 LSB (4.8 mV) at full scale, so it can be used in a wide range of analog and digital The amount of conversion circuit. The limit parameters of the TLC1549 in the operating temperature range: Power supply voltage range: -0.5 V to 6.5 V; 125°C input voltage range: -0.3 V~VCC+0.3 V; Output voltage range: -0.3~VCC+0.3 V; Positive reference voltage: VCC + 0.1 V; Negative reference voltage: -0.1 V; Peak input current: +20 mA; Peak total input current: ±30 mA; Operating temperature range: TLC1549M is -55 °C ~ 125 °C, TLC1549C is 0 °C ~ 70 °C, TLC1549I is -40 °C ~ 85 °C. 2 Working principle The TLC1549 has six serial interface timing modes defined by the I/O CLOCK period and CS. According to the functional structure and working sequence of TLC1549, its working process can be divided into three stages: analog sampling, analog conversion and digital transmission. Figure 3 shows the timing diagram of TLC1549. 2.1 Input analog sampling On the falling edge of the third I/O CLOCK, the input analog starts sampling, the sample lasts for 7 I/O CLOCK cycles, and the sampled value is latched on the 10th I/O CLOCK falling edge. 2.2 Input analog conversion For continuous successive approximation analog-to-digital converter TLC1549, the CMOS threshold detector determines the A/D conversion by detecting the charging voltage of a series of capacitors. Each bit of the digital quantity is shown in Figure 4. In the first phase of the conversion process, the analog input simultaneously turns off SC and ST for charge sampling, which causes the sum of the charging voltages of all capacitors to reach the input voltage of the analog-to-digital converter. The second phase of the conversion process turns on all SC and ST, and the CMOS threshold detector determines each bit to be close to the reference voltage by identifying the voltage of each capacitor. In this process, 10 capacitors are detected one by one until the tens digit of the conversion is determined. The detailed steps are as follows: the threshold detector detects the voltage of the first capacitor (weight=512), and the node 512 of the capacitor is connected to REF+. In a ladder network, the equivalent nodes of other capacitors are connected to REF-. If the total node voltage is greater than the threshold detector voltage (approximately half of VCC), "0" is sent to the output register, at which point the 512-weight capacitor is connected to REF-. After the inversion, it is "1", that is, the highest MSB is 1; if the voltage of the total node is less than the voltage of the threshold detector (about half of VCC), "1" is sent to the output register, at this time 512-weight The capacitor is connected to REF+, which is “0†after inversion and stored as the MSB of the highest bit. For 256-weight capacitors and 128-weight capacitors, the repeated operation of continuous successive approximation is also performed until all digital quantities from the high (MSB) to the low (LSB) are determined, which is the initial analog voltage digital. The entire conversion process adjusts VREF+ and VREF1 so that the voltage (VZT) that transitions from the digital 0 to 1 is 0.002 4 V, and the full-scale trip voltage (VFT) is 4.908 V, which is 1 LSB="4".8 mV. 2.3 Digital transmission When chip select CS changes from low to high, I/O CLOCK is disabled and the tri-state serial output DATA OUT of the A/D conversion result is in a high-impedance state; when the serial interface pulls CS to active, CS When going from high to low, CS resets the internal clock, controls and enables DA-TA OUT and I/O CLOCK, allowing I/O CLOCK to operate and DATA OUT out of high impedance. The serial interface supplies the input/output clock sequence to the I/O CLOCK and receives the last conversion result. First, the highest bit corresponding to the digital value of the previous conversion result is removed. The falling edge of the next I/O CLOCK drives the DATA OUT output to the next highest bit corresponding to the digital value of the previous conversion result. The falling edge of the ninth I/OCLOCK will be driven in order. DATA OUT outputs the lowest bit of the last conversion result digital, the 10th I/OCLOCK falling edge, DATA OUT outputs a low level for the serial interface to transmit more than 10 clocks; I/O CLOCK slave host serial interface Receives an input sequence of 10 to 16 clocks in length. On the falling edge of CS, the MSB of the last conversion appears on the DATA OUT side. The 10-bit digital is sent to the host serial interface via DATA OUT. In order to start the transfer, a minimum of 10 clock pulses is required. If the I/OCLOCK transfer is greater than 10 clocks, then on the falling edge of the 10th clock, the internal logic pulls DATA OUT low to ensure that the remaining bits are cleared. During the normal conversion cycle, that is, the high-to-low transition of the CS terminal during the specified time period can terminate the cycle, and the device returns to the initial state (the contents of the output data register remain as the last conversion result). Since the output data may be corrupted, care should be taken to prevent CS from pulling low when the conversion is complete. 3 example application and programming In practice, a function module needs to convert the analog voltage into a digital quantity, which is stored in the EEPROM after being processed by the single chip microcomputer. Use P1.7 as the chip select terminal ADCS, P1.6 as the data output terminal AD-DATA, and P1.5 as the clock terminal ADCLK. Figure 5 shows the application schematic of the A/D serial interface. For larger programs, structured programming should be used to divide the entire program into several modules according to functions. Different modules perform different functions, which makes the entire application system program clear and easy to debug and maintain. The program code is given below: 4 Conclusion The A/D serial output design not only improves the accuracy of analog-to-digital conversion, but also has immunity to interference and saves a lot of components and printed circuit board space. This system design has been successfully applied to data measurement in industrial field control systems. Mini relay is a classification of Signal Relay, which is commonly used in automatic control system. It is generally used to connect and disconnect circuits, and is an important part of automatic control and remote control circuits. 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